Loss of synchronization during communications in a digital communication system such as a second generation cordless telephone (CT2) system creates unwanted problems to system users. Loss of synchronization can be induced by selective multi-path fading, fiat fading, weak signals, as well as other well known communication phenomena.
Rapid timing fluctuations of recovered baseband data induced as a result of selective multi-path fading on a communication channel have been well documented in the literature. Within a CT2 system, timing induced errors may be controlled to some extent by digital phase lock loop (DPLL) circuits. However, in a selective multi-path fading environment, baseband timing may shift by more than .+-.0.5 bit without substantial eye closure (degradation in signal quality). This gives rise to the possibility of bit slippage which results in a loss of synchronization.
When a typical independent wideband first order DPLL is used in a selective multi-path fading environment, the instantaneous receive baseband timing can fluctuate with respect to an absolute reference as a result of time varying channel conditions. This phenomena is illustrated in the graph of FIG. 1 where the instantaneous recovered timing of the wide bandwidth recovered clock 106 with respect to receive baseband data timing 102 are compared to a reference 104. The first order wideband DPLL recovered timing 106 can track the instantaneous baseband timing 102 closely and thus track the received data transitions well within predetermined error limits 108 for muting. However, an abrupt fluctuation of the instantaneous receive baseband timing 102 exceeding phase error limit 108 at point 110 is capable of causing the first order wideband DPLL to track over to an adjacent bit which results in a loss of synchronization. In CT2 systems, this results in a lengthy interruption in voice communication while the system re-synchronizes.
When using a typical independent narrowband second order DPLL in a selective multi-path fading environment, the second order narrowband DPLL independently compensates for the frequency offset between a fixed part (master) and reference timers in a portable part (slave), which then allows recovered timing tracking with very narrow loop bandwidths. While this mode of operation eliminates the problems encountered with the first order wideband loop (loss of synchronization due to bit slippage), the capability of tracking receive baseband timing fluctuations is highly limited. This phenomena is illustrated in the graph of FIG. 2 where the instantaneous recovered timing of the narrow bandwidth recovered clock 206 with respect to receive baseband data timing 202 are compared to a reference 204. Instantaneous receive baseband timing 202 exceeds phase error limit 208 at points 210 which can result in multiple short mutes that occur from errors between the second order narrowband DPLL and the receive baseband timing.
Hence there is a need for an improved DPLL apparatus and method that maintains synchronization and reduces the occurrences of mutes in a system subjected to such problems as multi-path fading, weak signals, interference, and fiat fading.